This invention relates to semiconductor memory devices, and more particularly to an electrically-erasable, electrically-programmable ROM (read-only-memory) of the floating-gate type, and to a method for making such a device.
EPROMs, or electrically-programmable ROMs, are field-effect devices with a floating-gate structure. An EPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing high current through the source-drain path and charging of the floating gate by hot electrons. The EPROM type of device is erased by ultraviolet light, which requires a device package having a quartz window above the semiconductor chip. Packages of this type are expensive in comparison with the plastic packages ordinarily used for other memory devices such as DRAMs (dynamic-random-access-memories). For this reason, EPROMs are generally more expensive than plastic-packaged devices. EPROM devices of this type, and methods of manufacture, are disclosed in U.S. Pat. Nos. 3,984,822; 4,142,926; 4,258,466; 4,376,947; 4,326,331; 4,313,362; or 4,373,248; for example. Of particular interest to this invention is U.S. Pat. No. 4,750,024, issued Jun. 7, 1988 and filed Feb. 18, 1986 by John F. Schreck and assigned to Texas Instruments Incorporated, where an EPROM is shown made by a method similar to that of U.S. Pat. No. 4,258,466; but with an offset floating gate.
EEPROMs, or electrically-erasable, electrically-programmable ROMs, have been manufactured by various processes, usually requiring a much larger cell size than standard EPROMs, and requiring more complex manufacturing processes. EEPROMs can be mounted in opaque plastic packages that reduce the packaging cost. Nevertheless, EEPROMs have been more expensive on a per-bit basis, in comparison with EPROMs, due to larger cell size and to more complex manufacturing processes.
Flash EEPROMs have the advantage of smaller cell size in comparison with standard EEPROMs because the cells are not erased individually. Instead, the array of cells is erased in bulk.
Currently available flash EEPROMs require two power supplies, one for programming and erasing and another for reading. Typically, a 12-volt power supply is used for programming and erasing and a 5-volt power supply is used during read operations. It is desirable, however, to employ a single relatively low-voltage supply for all of the programming, erasing and reading operations.
The EEPROMs disclosed in co-pending U.S. patent applications No. 07/494,060, now U.S. Pat. No. 5,012,307 and No. 07/494,051, now U.S. Pat. No. 5,017,980, filed herewith, provide a greatly improved structure and method for making cells having reduced size and ease of manufacture, resulting in a device requiring one relatively low-voltage (perhaps +5 v) power supply to the chip. Nevertheless, in some situations improvement in the break-down voltage at the source-to-substrate interface beneath the edge of the source region, as explained below, is believed to be possible in such devices.
It is the principal object of the invention to provide an EEPROM in which the tunnel is self-aligned so that manufacture is facilitated and reliability is enhanced. Further, it is an object to provide an EEPROM having reduced cell size and having improved coupling between control gate and floating gate. Other objects include provision of a cell resistant to bitline stress, which is the deprogramming of a programmed cell during write operations, and include improved field-plate breakdown voltage. Another object of this invention is to provide an electrically programmable memory, or an electrically-erasable and electrically-programmable memory, which can be packaged in a less expensive opaque plastic package. Another object is to provide an improved method of making an electrically erasable memory, including the use of a method for forming a tunnel window having dimensions smaller than the minimum spacing allowed by usual design rules, allowing the cell size to be smaller and facilitating scaling. It is also an object to provide a non-volatile memory that uses a single low-voltage external supply for both programming and erasing, allowing the memory device to be compatible with on-board or in-circuit programming where systems have a single external power supply. An additional does not require high current for both programming and erasing.